In many personal computers, a host CPU transfers data from and to a video graphics memory through a port of the memory which is mapped to the input/output (I/O) port of the CPU. A video controller that controls reading from and writing to the memory contains a video memory address pointer that selects the memory location that is being mapped to the port, which pointer is automatically updated whenever the CPU accesses the I/O mapped memory port. Thus as data is read from or written to the memory, data which corresponds in width to the CPU port is read from or written to the video memory at video memory addresses that begin at new address locations pointed to by the pointer, for each successive read or write.
The host expansion bus typically transfers data at 8, 16 or 32 bits at a time, while the video memory bus is typically 32 to 64 bits in width. Therefore a protocol is used to determine when the address pointer should be incremented. In this protocol, the address pointer is incremented whenever the most significant byte is accessed by the host CPU. This relies on the assumption that during a multi-byte data transfer, the host CPU always accesses the most significant byte last, and assures that all the less significant bytes will have already been transferred when the most significant byte is accessed.
However it has been found that when executing 32 bit input/output instructions on personal computer motherboards, this convention is not always followed, i.e. the most significant byte is not the last byte accessed. For this reason, video driver programs cannot use 32 bit input/output instructions, since incorrect data can be transferred. To ensure that the instructions will be carried out with reliability, video driver programs have relied on 16 bit input/output instructions. Such instructions clearly transfer data much slower than 32 bit input/output instructions, and results in significant degradation in performance from the capability of the computer.